Optimization Considerations for Short Channel Poly-Si 1T-DRAM

Short-Channel Poly-Si Thin-Film Transistors with Ultrathin Channel

The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM). Recently, the tunneling FET (TFET) is applied in DRAM cell due to the low off-state current and high switching ratio. The dual-gate TFET (DG-TFET) DRAM cell with the capacitorless structure ...

Novel 1T DRAM Cell for Low-Voltage Operation and Long Data Retention Time

A novel one-transistor dynamic random access memory (1T DRAM) cell has been proposed for a low-voltage operation and longer data retention time. The proposed 1T DRAM cell has three features compared with a conventional 1T DRAM cell: low body doping concentration, a recessed gate structure, and a P poly-Si gate. Simulation results show that the proposed 1T DRAM cell has < 1-ns program time and >...

Short channel effects in regioregular poly(thiophene) thin film transistors

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channel estimation for mimo-ofdm systems

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